Digital phase lock loops (DPLLs) are commonly used to create oscillatory signals in phase with, but at frequency multiples or divisors of, reference oscillations. Sigma-Delta analog to digital (A/D) converters commonly use DPLLs to generate the high frequency sampling oscillations used in the conversion process.
Another application of a DPLL is in a digital phone system wherein digital transmissions are sent from a base unit and received by a portable unit. On a periodic basis, the base unit transmits data frames to the portable unit. From the data frame, a radio frequency transceiver within the portable unit constructs a reference oscillation from the data frames. The reference oscillation provides a basis for a communication processor in the portable unit to receive digital data and also to transmit digital data that is synchronized to the base unit. The communication processor converts the digital data to analog data that is conveyed to a user and also receives analog data from a user, converts the data to a digital format, and transmits the data to the base unit in a synchronized fashion. To ensure proper synchronization, the communication processor requires a high frequency sampling signal that is in phase with the reference oscillation, thus it incorporates a DPLL.
The DPLL located in the portable unit creates the sampling signal that the communication processor uses to synchronize with the reference oscillation. The DPLL typically includes a phase detector, a loop filter, and a digital oscillator. In operation, the digital oscillator constructs a first oscillation from a fixed frequency clock. Typically, the fixed frequency clock is of a frequency on the order of 10 MHz and the first oscillation is of a frequency on the order of 1 MHz. The first oscillation is then provided as an input to the divider which creates both a feedback oscillation and a sampling signal that is used by other circuitry in the system. The digital oscillator and divider are designed such that the frequency of the feedback oscillation is of the same frequency as the reference oscillation. Thus, not accounting for drift and variations in the frequencies of the signals, the reference and feedback oscillations are of an identical frequency and the control function of the DPLL is to force the feedback oscillation in phase with the reference oscillation. In this manner, the sampling signal will also be in phase with the reference oscillation.
However, due to inaccuracies in crystal oscillators of the reference oscillation clock and the fixed frequency clock, the design frequency of the DPLL usually varies from the frequency of the reference oscillation. Over time, the frequency differences of the signals appears as phase shifts between the reference and feedback oscillations. Thus, a control function of the DPLL is to shift the feedback oscillation so as to force it in phase with the reference oscillation. This is accomplished with the phase detector which compares the feedback oscillation created by the DPLL to the incoming reference oscillation. If the reference oscillation precedes the feedback oscillation in time, the phase detector outputs a late signal. If the feedback oscillation precedes the reference oscillation in time, the phase detector outputs an early signal. The early signal provides a count-up signal to a counter of the loop filter and the late signal provides a countdown signal to the counter. When the count goes above a positive count threshold, the loop filter issues a retard signal to the digital oscillator. Alternatively, when the count goes below a negative count threshold, the loop filter issues an advance signal to the digital oscillator.
The digital oscillator, which includes a counter and a decoder, outputs the first oscillation when the counter reaches a certain count. When the digital oscillator receives an advance signal, the first oscillation is produced upon a lower count. Alternatively, when the digital oscillator receives a retard signal, the first oscillation is produced upon a higher count. Thus, a rising edge of the first oscillation is shifted with respect to a previous rising edge of the first oscillation so that the phase of the first oscillation is closer to the phase of the reference oscillation.
While shifting the first oscillation causes it to be in phase with the reference oscillation, the sampling signal also is shifted with respect to the reference oscillation. This shift of the sampling signal appears as noise in the sampling signal and resultantly causes noise in the coupled circuitry. Without filtering in the control of the DPLL, shifts in the sampling signal occur often and the sampling signal has significant "jitter". Resultantly, significant noise may be introduced into the sampling process.
Therefore, a need exists for a controlling circuit that reduces the injected noise in DPLLs when frequency corrections are being made.